Increased circuit density is an ongoing goal of manufacturers of semiconductor devices. One long-favored configuration is an assembly of vertically stacked semiconductor dice, at least some of which are interconnected electrically and the stacked die assembly being mechanically and electrically connected to higher level packaging, such as an interposer or other substrate bearing conductive traces.
One configuration employing a plurality of stacked semiconductor dice is a MicroPillar Grid Array (“MPGA”) package. Such a package comprises a stack of a plurality (for example, four (4)) of dynamic random access (DRAM) semiconductor memory dice vertically interconnected from an uppermost die to a lowermost die, and a plurality of conductive pillars extending from the underside of the lowermost memory die for connection to a logic die or a System on a Chip (SoC) die.
The provider of the logic die or the SoC die conventionally mounts their device to an interposer, such as a ball grid array (BGA) substrate, the logic or SoC die including conductive through vias for connection to the conductive pillars on the underside of the MPGA. The MPGA is mounted to the logic die or SoC die on the interposer, and the assembly is then overmolded with an encapsulant into a finished BGA package.
The aforementioned configuration, implemented as a so-called “Wide I/O” memory device, enables fast memory access, and reduces power requirements.
The end product finds application, among others, in mobile electronic devices such as so-called “smart phones” exemplified by BLACKBERRY® devices, IPHONE® devices, and DROID® devices, among others.